標題: Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
作者: Ker, MD
Chuang, CH
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: electrostatic discharge (ESD);ESD protection circuit;mixed-voltage I/O buffer;silicon controlled rectifier (SCR)
公開日期: 1-八月-2002
摘要: A new electrostatic discharge (ESD) protection circuit, using the stacked-nMOS triggered silicon controlled rectifier (SNTSCR) as the ESD clamp device, is designed to protect the mixed-voltage I/O buffers of CMOS ICs. The new proposed ESD protection circuit, which combines the stacked-nMOS structure with the gate-coupling circuit technique into the SCR device, is fully compatible to general CMOS processes without causing the gate-oxide reliability problem. Without using the thick gate oxide, the experimental results in a 0.35-mum CMOS process have proven that the human-body-model ESD level of the mixed-voltage I/O buffer can be successfully increased from the original similar to2 kV to >8 kV by using this proposed ESD protection circuit.
URI: http://dx.doi.org/10.1109/JSSC.2002.800933
http://hdl.handle.net/11536/28649
ISSN: 0018-9200
DOI: 10.1109/JSSC.2002.800933
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 37
Issue: 8
起始頁: 1046
結束頁: 1055
顯示於類別:期刊論文


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