標題: | BINARY PARTITION ALGORITHMS AND VLSI ARCHITECTURES FOR MEDIAN AND RANK ORDER FILTERING |
作者: | LEE, CL JEN, CW 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 1-Sep-1993 |
摘要: | A class of selection algorithms by binary partition is very efficient for median and rank order filtering. A unified discussion of these algorithms is presented. Binary partition algorithms have better time-area complexity than sorting methods. Counting, firing, and updating are three basic steps. A generic structure is proposed to realize these algorithms. They can be implemented by simple and regular modules in VLSI. |
URI: | http://dx.doi.org/10.1109/78.236516 http://hdl.handle.net/11536/2867 |
ISSN: | 1053-587X |
DOI: | 10.1109/78.236516 |
期刊: | IEEE TRANSACTIONS ON SIGNAL PROCESSING |
Volume: | 41 |
Issue: | 9 |
起始頁: | 2937 |
結束頁: | 2942 |
Appears in Collections: | Articles |
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