| 標題: | Ultra-shallow junction formation using implantation through capping nitride layer on source/drain extension |
| 作者: | Hsien, LJ Chan, YL Chao, TS Jiang, YL Kung, CY 電子物理學系 Department of Electrophysics |
| 關鍵字: | shallow junction;nitride;CMOS |
| 公開日期: | 1-Jul-2002 |
| 摘要: | Method for forming ultra-shallow p(+)/n is demonstrated for 0.15 mum p-type metal-oxide-semiconductor field-effect transistor (pMOSFET). The approach includes a capping ultra-thin nitride on the source/drain extension regions followed by a low energy source/drain (S/D) extension implantation. Ultra shallow p(+)/n junctions can be obtained with depth of 27 nm and sheet resistivity of 1007 Omega/square. |
| URI: | http://dx.doi.org/10.1143/JJAP.41.4519 http://hdl.handle.net/11536/28705 |
| ISSN: | 0021-4922 |
| DOI: | 10.1143/JJAP.41.4519 |
| 期刊: | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS |
| Volume: | 41 |
| Issue: | 7A |
| 起始頁: | 4519 |
| 結束頁: | 4520 |
| Appears in Collections: | Articles |
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