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dc.contributor.authorKer, MDen_US
dc.contributor.authorChen, TYen_US
dc.date.accessioned2014-12-08T15:43:05Z-
dc.date.available2014-12-08T15:43:05Z-
dc.date.issued2002-01-01en_US
dc.identifier.issn0304-3886en_US
dc.identifier.urihttp://dx.doi.org/10.1016/S0304-3886(01)00154-1en_US
dc.identifier.urihttp://hdl.handle.net/11536/29151-
dc.description.abstractA design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices is developed in this work to keep the total input capacitance almost constant, even if the analog signal has a varying input voltage. An analog ESD protection circuit has been designed to solve ESD protection challenge on the analog pins for high-frequency applications. The device dimension (W/L) of ESD protection device connected to the I/O pad can be reduced to only 50 mum/0.5 mum in a 0.35-mum silicided CMOS process, but it can sustain HBM (MM) ESD level up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only similar to0.4 pF for high-frequency applications. This input capacitance can be further reduced if the ESD protection devices are designed with smaller device dimensions. Moreover, by using the optimized layout design to draw the layout of ESD protection NMOS and PMOS devices, the voltage-dependent variation on input capacitance of this analog ESD protection circuit can be kept below 1% under an input voltage swing of 1 V. With such almost constant input capacitance, the nonlinear distortion causing by on-chip ESD protection circuit can be minimized for high-precision applications. (C) 2002 Elsevier Science B.V. All rights reserved.en_US
dc.language.isoen_USen_US
dc.subjectESDen_US
dc.subjectanalog circuiten_US
dc.subjectinput capacitanceen_US
dc.titleLayout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuiten_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1016/S0304-3886(01)00154-1en_US
dc.identifier.journalJOURNAL OF ELECTROSTATICSen_US
dc.citation.volume54en_US
dc.citation.issue1en_US
dc.citation.spage73en_US
dc.citation.epage93en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000173189800006-
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