標題: | Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications |
作者: | Ker, MD Chen, TY Wu, CY Chang, HH 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2000 |
摘要: | An on-chip ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-precision applications. A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices has been developed to keep the total input capacitance almost constant (within 1% variation), even if the analog signal has an input dynamic range of 1V. The device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (mu m/mu m) in a 0.35-mu m silicided CMOS process, but it can sustain the HEM (MM) ESD level of up to 6kV (400V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only similar to 1.0 pF (including the bond pad capacitance) for high-frequency applications. |
URI: | http://hdl.handle.net/11536/19303 |
期刊: | ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL V: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY |
起始頁: | 61 |
結束頁: | 64 |
顯示於類別: | 會議論文 |