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dc.contributor.authorLee, TGYen_US
dc.contributor.authorTseng, TYen_US
dc.contributor.authorWong, SCen_US
dc.contributor.authorYang, CJen_US
dc.contributor.authorLiang, MSen_US
dc.contributor.authorCheng, HCen_US
dc.date.accessioned2014-12-08T15:43:09Z-
dc.date.available2014-12-08T15:43:09Z-
dc.date.issued2001-12-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://hdl.handle.net/11536/29211-
dc.description.abstractNew analytical models for estimating the delay time of single line and coupled interconnect for ramp input waveform are derived, The accuracy of the signal delay time and crosstalk noise voltage models for various driver resistances, loading capacitances, and input-ramping rates has also been verified by simulation program with integrated circuit emphasis (SPICE) simulation. Based on the delay and crosstalk models, interconnect optimization design can be discussed thoroughly. The proposed guaranteed-performance interconnect design method is also discussed. These models are useful for performance estimation and layout optimization in VLSI synthesis as well as process optimization in technology development.en_US
dc.language.isoen_USen_US
dc.subjectclosed-form modelen_US
dc.subjectinterconnecten_US
dc.subjectmodelen_US
dc.subjectdelayen_US
dc.subjectcrosstalken_US
dc.subjectoptimizationen_US
dc.titleGeneralized interconnect delay time and crosstalk models: I. Applications of interconnect optimization designen_US
dc.typeArticleen_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERSen_US
dc.citation.volume40en_US
dc.citation.issue12en_US
dc.citation.spage6686en_US
dc.citation.epage6693en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000175190700002-
dc.citation.woscount1-
Appears in Collections:Articles


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