標題: Testing Methodology of Embedded DRAMs
作者: Chang, Chi-Min
Chao, Mango C. -T.
Huang, Rei-Fu
Chen, Ding-Yuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2008
摘要: The embedded-DRAM testing mixes up the techniques used for DRAM testing and SRAM testing since an embedded-DRAM core combines DRAM cells with an SRAM interface (the so-called IT-SRAM architecture). In this paper we first present our test algorithm for embedded-DRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the embedded-DRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. The experimental results art? collected based on I-lot wafers with an 16Mb embedded DRAM core.
URI: http://hdl.handle.net/11536/2930
ISBN: 978-1-4244-2402-3
ISSN: 1089-3539
期刊: 2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS
起始頁: 647
結束頁: 655
顯示於類別:會議論文