標題: | Wafer rework strategies at the photolithography stage |
作者: | Sha, DY Hsieh, LF Chen, KJ 工業工程與管理學系 Department of Industrial Engineering and Management |
關鍵字: | rework strategy;mother lot;child lot;cycle time;utilization;simulation |
公開日期: | 1-Jun-2001 |
摘要: | Defective wafers are often seen during the semiconductor manufacturing process. Technically, there is no known remedy for a defective wafer. However, at the photolithography phase of semiconductor manufacturing, the defective wafers can be reworked to reduce the manufacturing cost significantly. In this paper, when comparing the three rework strategies that were proposed by Zargar, we pinpoint the disadvantages of each and offer two other strategies. We assess the advantages and disadvantages of the five rework strategies of each reworked batch according to total cycle time, the quantity of work-in-process, each machine's utilization rate, the utilization rate of photolithography, and the average length of queues for photolithography. Through simulations and statistics, the fifth strategy is shown to be superior to the first four and most suitable for wafer manufacturing. Significance: At the photolithography stage, the processing relation between lot and lot should be considered. Thus, how to schedule reworking in order to reduce the effect on waiting lots is a crucial issue for wafer manufacturing management. |
URI: | http://hdl.handle.net/11536/29580 |
ISSN: | 1072-4761 |
期刊: | INTERNATIONAL JOURNAL OF INDUSTRIAL ENGINEERING-THEORY APPLICATIONS AND PRACTICE |
Volume: | 8 |
Issue: | 2 |
起始頁: | 122 |
結束頁: | 130 |
Appears in Collections: | Articles |