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dc.contributor.authorWu, CYen_US
dc.contributor.authorYen, WCen_US
dc.date.accessioned2014-12-08T15:44:19Z-
dc.date.available2014-12-08T15:44:19Z-
dc.date.issued2001-01-01en_US
dc.identifier.issn1057-7122en_US
dc.identifier.urihttp://dx.doi.org/10.1109/81.903184en_US
dc.identifier.urihttp://hdl.handle.net/11536/29923-
dc.description.abstractBased on the basic device physics of the neuron-bipolar junction transistor (nu BJT), a new compact cellular neural network (CNN) structure called the nu BJT CNN is proposed and analyzed. In the nu BJT CNN, both nu BJT and lambda bipolar transistor realized by parasitic p-n-p BJTs in the CMOS process are used to implement the neuron whereas the coupling MOS resistors are used to realize the symmetric synapse weights among various neurons. Thus it has the advantages of small chip area and high integration capability, Moreover, the proposed symmetric nu BJT CNN can be easily designed to achieve large neighborhood without extra interconnection. By adding a metal-layer optical window to the nu BJT, the nu BJT can be served as the phototransistor, and the nu BJT CNN can receive optical images as initial state inputs or external inputs. The correct functions of the nu BJT CNNs in noise removal, hole filling, and erosion have been successfully verified in HSPICE simulation. An experimental chip containing a 32 x 32 nu BJT CNN and a 16 x 16 nu BJT CNN with phototransistor design, has been designed and fabricated in 0.6-mum single-poly triple-metal n-well CMOS technology. The fabricated chips have the cell state transition time of 0.8 mus and the static power consumption of 60 muW/cell. The area density can be as high as 1270 cells/mm(2). The measurement results have also confirmed the correct functions of the proposed nu BJT CNNs.en_US
dc.language.isoen_USen_US
dc.subjectcellular neural networken_US
dc.subjectnu BJTen_US
dc.subjectlarge neighborhooden_US
dc.titleA new compact neuron-bipolar junction transistor (nu BJT) cellular neural network (CNN) structure with programmable large neighborhood symmetric templates for image processingen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/81.903184en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONSen_US
dc.citation.volume48en_US
dc.citation.issue1en_US
dc.citation.spage12en_US
dc.citation.epage27en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000166993700002-
dc.citation.woscount15-
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