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dc.contributor.authorSHUNG, CBen_US
dc.contributor.authorLIN, HDen_US
dc.contributor.authorCYPHER, Ren_US
dc.contributor.authorSIEGEL, PHen_US
dc.contributor.authorTHAPAR, HKen_US
dc.date.accessioned2014-12-08T15:04:32Z-
dc.date.available2014-12-08T15:04:32Z-
dc.date.issued1993-05-01en_US
dc.identifier.issn0090-6778en_US
dc.identifier.urihttp://dx.doi.org/10.1109/26.225495en_US
dc.identifier.urihttp://hdl.handle.net/11536/3022-
dc.description.abstractIn the previous paper, we established the theoretical foundations of a new class of area-efficient architectures for the Viterbi algorithm. In this paper, we will show area-efficient architectures for practical codes to illustrate the design procedures and demonstrate the favorable area-time tradeoff results. Three examples from convolutional codes, matched-spectral-null (MSN) trellis codes, and Ungerboeck codes will be presented. We will also discuss the application of our area-efficient techniques to codes with a very large numbers of states, codes with time-varying trellises, and a programmable Viterbi decoder.en_US
dc.language.isoen_USen_US
dc.titleAREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .2. APPLICATIONSen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/26.225495en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMMUNICATIONSen_US
dc.citation.volume41en_US
dc.citation.issue5en_US
dc.citation.spage802en_US
dc.citation.epage807en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1993LR65600020-
dc.citation.woscount19-
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