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dc.contributor.authorChang, CYen_US
dc.contributor.authorChang, SJen_US
dc.contributor.authorChao, TSen_US
dc.contributor.authorWu, SDen_US
dc.contributor.authorHuang, TYen_US
dc.date.accessioned2014-12-08T15:44:51Z-
dc.date.available2014-12-08T15:44:51Z-
dc.date.issued2000-09-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://hdl.handle.net/11536/30284-
dc.description.abstractThe effects of narrow channel width on the threshold voltage of deep submicron silicon-on-insulator (SOI) nMOSFETs with LOGOS isolation have been investigated. The reverse narrow channel effect (RNCE) in SOI devices is found to be dependent on the thickness of the active silicon film. A thinner silicon film is found to depict less threshold voltage fall-off. These results can be explained by a reduced oxide/silicon interface area in the transistor width direction, thus the boron segregation due to silicon interstitials with high recombination rate is reduced.en_US
dc.language.isoen_USen_US
dc.subjectreverse narrow channel effect (RNCE)en_US
dc.subjectsilicon-on-insulator (SOI)en_US
dc.titleReduced reverse narrow channel effect in thin SOI nMOSFETsen_US
dc.typeArticleen_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume21en_US
dc.citation.issue9en_US
dc.citation.spage460en_US
dc.citation.epage462en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000089132500014-
dc.citation.woscount4-
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