完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, CY | en_US |
dc.contributor.author | Chang, SJ | en_US |
dc.contributor.author | Chao, TS | en_US |
dc.contributor.author | Wu, SD | en_US |
dc.contributor.author | Huang, TY | en_US |
dc.date.accessioned | 2014-12-08T15:44:51Z | - |
dc.date.available | 2014-12-08T15:44:51Z | - |
dc.date.issued | 2000-09-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/30284 | - |
dc.description.abstract | The effects of narrow channel width on the threshold voltage of deep submicron silicon-on-insulator (SOI) nMOSFETs with LOGOS isolation have been investigated. The reverse narrow channel effect (RNCE) in SOI devices is found to be dependent on the thickness of the active silicon film. A thinner silicon film is found to depict less threshold voltage fall-off. These results can be explained by a reduced oxide/silicon interface area in the transistor width direction, thus the boron segregation due to silicon interstitials with high recombination rate is reduced. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | reverse narrow channel effect (RNCE) | en_US |
dc.subject | silicon-on-insulator (SOI) | en_US |
dc.title | Reduced reverse narrow channel effect in thin SOI nMOSFETs | en_US |
dc.type | Article | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 21 | en_US |
dc.citation.issue | 9 | en_US |
dc.citation.spage | 460 | en_US |
dc.citation.epage | 462 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000089132500014 | - |
dc.citation.woscount | 4 | - |
顯示於類別: | 期刊論文 |