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DC 欄位語言
dc.contributor.authorChang, YJen_US
dc.contributor.authorLee, CLen_US
dc.contributor.authorChen, JEen_US
dc.contributor.authorSu, CCen_US
dc.date.accessioned2014-12-08T15:44:52Z-
dc.date.available2014-12-08T15:44:52Z-
dc.date.issued2000-09-01en_US
dc.identifier.issn1016-2364en_US
dc.identifier.urihttp://hdl.handle.net/11536/30292-
dc.description.abstractIn this paper, a simple behavior-level fault model, which is able to represent the faulty behavior of the closed-loop operational amplifier (OP), is presented. The fault model, derived from the macro equivalent circuit of the OP but verified with transistor level simulation, consists of the offset fault and the limited-current fault. It can represent the faulty behavior of the dosed loop OP of all the transistor parametric (soft) faults and many of the catastrophic (hard) faults. Due to its simplicity, the proposed fault model (1) significantly reduces the complexity of fault simulation, and (2) makes closed-form analysis of the faulty behavior of the closed loop OP feasible when the closed loop OP is used as a basic building block of a complicated circuit. Although derived for DC, it can also be applied to AC fault analysis.en_US
dc.language.isoen_USen_US
dc.subjectfault simulationen_US
dc.subjectfault modelen_US
dc.subjectmacro-modelingen_US
dc.subjectoperational amplifieren_US
dc.subjectanalog/mixed testingen_US
dc.subjectMonte Carloen_US
dc.titleA behavior-level fault model for the closed-loop operational amplifieren_US
dc.typeArticleen_US
dc.identifier.journalJOURNAL OF INFORMATION SCIENCE AND ENGINEERINGen_US
dc.citation.volume16en_US
dc.citation.issue5en_US
dc.citation.spage751en_US
dc.citation.epage766en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000089367400007-
dc.citation.woscount6-
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