標題: High-speed booth encoded parallel multiplier design
作者: Yeh, WC
Jen, CW
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: final adder;Booth encoding;multiple-level conditional-sum adder;and parallel multiplier
公開日期: 1-七月-2000
摘要: This paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder according to the given cell properties and input delay profile. Compared with a binary tree-based conditional-sum adder, the speed performance improvement is up to 25 percent. On average, the design developed herein reduces the total delay by 8 percent for parallel multiplier. The whole design has been verified by gate level simulation.
URI: http://hdl.handle.net/11536/30400
ISSN: 0018-9340
期刊: IEEE TRANSACTIONS ON COMPUTERS
Volume: 49
Issue: 7
起始頁: 692
結束頁: 701
顯示於類別:期刊論文


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