完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wu, YH | en_US |
dc.contributor.author | Chin, A | en_US |
dc.date.accessioned | 2014-12-08T15:45:06Z | - |
dc.date.available | 2014-12-08T15:45:06Z | - |
dc.date.issued | 2000-07-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/55.847377 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/30424 | - |
dc.description.abstract | We have used a simple process to fabricate Si0.3Ge0.7/Si p-MOSFET's. The Si0.3Ge0.7 is formed using deposited Ge followed by 950 degrees C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. Hole mobility of 250 cm(2)/Vs is obtained from Si0.3Ge0.7 p-MOSFET that is similar to two times higher than Si control devices and results in a consequent substantially higher current drive. The 228 Angstrom Si0.3Ge0.7 thermal oxide grown at 1000 degrees C has a high breakdown field of 15 MV/cm, low interface trap density (D-it) of 1.5 x 10(11) eV(-1) cm(-2), and low oxide charge of 7.2 x 10(10) cm(-2). The source-drain junction leakage after implantation and 950 degrees C RTA is also comparable with Si counterpart. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | hole mobility | en_US |
dc.subject | P-MOSFET | en_US |
dc.subject | reliability | en_US |
dc.subject | SiGe | en_US |
dc.title | High temperature formed SiGeP-MOSFET's with good device characteristics | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/55.847377 | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 21 | en_US |
dc.citation.issue | 7 | en_US |
dc.citation.spage | 350 | en_US |
dc.citation.epage | 352 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000087898300008 | - |
dc.citation.woscount | 11 | - |
顯示於類別: | 期刊論文 |