標題: Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
作者: Ker, MD
Lo, WY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: electrostatic discharge (ESD);latch-up;ESD protection;circuit;diode string;SCR;leakage current;ESD bus
公開日期: 1-四月-2000
摘要: A new design on the diode string with very tow leakage current is proposed for using in the ESD clamp circuits across the power rails. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the Leakage current of this new diode string with six stacked diodes at 5-V (3.3-V) forward bias can be reduced to only 2.1 (1.07) nA at a temperature of 125 degrees C in a 0.35-mu m silicide CMOS process, whereas the previous designs have a leakage current in the order of mA, The total blocking voltage of this new design with NCLSCR can be linearly adjusted by changing the number of the stacked diodes in the diode string without causing latch-up danger across the power rails. From the experimental results, the human-body-model ESD level of the ESD clamp circuit with the proposed low-leakage diode string is greater than 8 kV in a 0.35-mu m silicide CMOS process by using neither the ESD-implantation nor the silicide-blocking process modifications.
URI: http://dx.doi.org/10.1109/4.839920
http://hdl.handle.net/11536/30607
ISSN: 0018-9200
DOI: 10.1109/4.839920
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 35
Issue: 4
起始頁: 601
結束頁: 611
顯示於類別:期刊論文


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