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dc.contributor.authorSHUNG, CBen_US
dc.contributor.authorLIN, HDen_US
dc.contributor.authorCYPHER, Ren_US
dc.contributor.authorSIEGEL, PHen_US
dc.contributor.authorTHAPAR, HKen_US
dc.date.accessioned2014-12-08T15:04:34Z-
dc.date.available2014-12-08T15:04:34Z-
dc.date.issued1993-04-01en_US
dc.identifier.issn0090-6778en_US
dc.identifier.urihttp://dx.doi.org/10.1109/26.223789en_US
dc.identifier.urihttp://hdl.handle.net/11536/3060-
dc.description.abstractThe Viterbi algorithm has been widely applied to many decoding and estimation applications in communications and signal processing. A state-parallel implementation is usually used in which one add-compare-select (ACS) unit is devoted to each state in the trellis. In this paper we present a systematic approach of partitioning, scheduling, and mapping the N trellis states to P ACS's, where N > P. The area saving of our architecture comes from the reduced number of both the ACS's and interconnection wires. The design of the ACS, path metric storage, and routing network is discussed in detail. The proposed architecture creates internal parallelism due to the ACS sharing, which can be exploited to increase the throughput rate by pipelining. Consequently, the area-efficient architecture offers a favorable (smaller) area-time product, compared to a state-parallel implementation. These results will be demonstrated by application examples in the accompanying paper.en_US
dc.language.isoen_USen_US
dc.titleAREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .1. THEORYen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/26.223789en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMMUNICATIONSen_US
dc.citation.volume41en_US
dc.citation.issue4en_US
dc.citation.spage636en_US
dc.citation.epage644en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1993LP11800018-
dc.citation.woscount34-
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