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dc.contributor.authorChang, Ming-Hungen_US
dc.contributor.authorChuang, Li-Puen_US
dc.contributor.authorChang, I-Mingen_US
dc.contributor.authorHwang, Weien_US
dc.date.accessioned2014-12-08T15:45:57Z-
dc.date.available2014-12-08T15:45:57Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-2596-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/30909-
dc.description.abstractA 300mV 20MHz-35OMHz low variation all-digital multiphase dual clock output generator with rapid self-calibration has been designed with UMC 90nm CMOS technology model. The PVT immunity properties of several classic delay elements in low voltage era have been studied. A low voltage calibration unit is also proposed to reduce the maximum multiphase error no larger than 120ps when delay-locked loop is operating at 40MHz/300mV. A novel static current-mirror-based phase blender is developed to provide wide range accurate twice multiphase information, and phase error is reduced by no more than 11.83%. The clock generator could provide more independent outputs by simply using additional edge combiner. The frequency and phase of output clock could be dynamically adjusted without relocking process. The total power dissipation of the all-digital multiphase dual digital clock output generator is 36 mu W at 40MHz/300mV.en_US
dc.language.isoen_USen_US
dc.titleA 300-mV 36-mu W Multiphase Dual Digital Clock Output Generator with Self-Calibrationen_US
dc.typeArticleen_US
dc.identifier.journalIEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGSen_US
dc.citation.spage97en_US
dc.citation.epage100en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000260931700019-
Appears in Collections:Conferences Paper