标题: | VLSI design for high-speed LZ-based data compression |
作者: | Chen, JM Wei, CH 电子工程学系及电子研究所 Department of Electronics Engineering and Institute of Electronics |
公开日期: | 1-十月-1999 |
摘要: | A simple real-time parallel architecture for CMOS VLSI implementation of a Ziv-Lempel data compression system is presented. This encoding system employs a linear systolic allay to find concurrently the matches between each input data character and its corresponding dictionary, and can easily achieve ideal compression ratio by cascading the chips of the encoding cell. A new encoding architecture is proposed to improve the encoding speed and reduce hardware complexity for the encoding cells. In addition, the number of memory accesses is reduced to save power consumption for high-speed applications. The encoder codes one character (more than eight bits) per encoding cycle. The clock rate by Verilog simulator can be constrained below 15ns using the Compass standard cell library for the 0.6 mu m CMOS process. |
URI: | http://dx.doi.org/10.1049/ip-cds:19990535 http://hdl.handle.net/11536/31061 |
ISSN: | 1350-2409 |
DOI: | 10.1049/ip-cds:19990535 |
期刊: | IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS |
Volume: | 146 |
Issue: | 5 |
起始页: | 268 |
结束页: | 278 |
显示于类别: | Articles |
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