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dc.contributor.authorWU, SLen_US
dc.contributor.authorLIN, TYen_US
dc.contributor.authorLEE, CLen_US
dc.contributor.authorLEI, TFen_US
dc.date.accessioned2014-12-08T15:04:37Z-
dc.date.available2014-12-08T15:04:37Z-
dc.date.issued1993-03-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/55.215128en_US
dc.identifier.urihttp://hdl.handle.net/11536/3110-
dc.description.abstractA low-temperature wafer loading and N2 preannealing process is used to grow a thin textured polysilicon oxide. The polyoxide grown on the heavily doped polysilicon film exhibits less oxide tunneling leakage current and higher dielectric strength when the top electrode is positively biased.en_US
dc.language.isoen_USen_US
dc.titleELECTRICAL CHARACTERISTICS OF TEXTURED POLYSILICON OXIDE PREPARED BY A LOW-TEMPERATURE WAFER LOADING AND N-2 PREANNEALING PROCESSen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/55.215128en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume14en_US
dc.citation.issue3en_US
dc.citation.spage113en_US
dc.citation.epage114en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1993KN76400006-
dc.citation.woscount18-
Appears in Collections:Articles


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