ELECTRICAL CHARACTERISTICS OF TEXTURED POLYSILICON OXIDE PREPARED BY A LOW-TEMPERATURE WAFER LOADING AND N-2 PREANNEALING PROCESS

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DC 欄位	值	語言
dc.contributor.author	WU, SL	en_US
dc.contributor.author	LIN, TY	en_US
dc.contributor.author	LEE, CL	en_US
dc.contributor.author	LEI, TF	en_US
dc.date.accessioned	2014-12-08T15:04:37Z	-
dc.date.available	2014-12-08T15:04:37Z	-
dc.date.issued	1993-03-01	en_US
dc.identifier.issn	0741-3106	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/55.215128	en_US
dc.identifier.uri	http://hdl.handle.net/11536/3110	-
dc.description.abstract	A low-temperature wafer loading and N2 preannealing process is used to grow a thin textured polysilicon oxide. The polyoxide grown on the heavily doped polysilicon film exhibits less oxide tunneling leakage current and higher dielectric strength when the top electrode is positively biased.	en_US
dc.language.iso	en_US	en_US
dc.title	ELECTRICAL CHARACTERISTICS OF TEXTURED POLYSILICON OXIDE PREPARED BY A LOW-TEMPERATURE WAFER LOADING AND N-2 PREANNEALING PROCESS	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/55.215128	en_US
dc.identifier.journal	IEEE ELECTRON DEVICE LETTERS	en_US
dc.citation.volume	14	en_US
dc.citation.issue	3	en_US
dc.citation.spage	113	en_US
dc.citation.epage	114	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1993KN76400006	-
dc.citation.woscount	18	-
顯示於類別：	期刊論文

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