Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Wang, Li-Rong | en_US |
dc.contributor.author | Chiu, Yi-Wei | en_US |
dc.contributor.author | Hu, Chia-Lin | en_US |
dc.contributor.author | Tu, Ming-Hsien | en_US |
dc.contributor.author | Jou, Shyh-Jye | en_US |
dc.contributor.author | Lee, Chung-Len | en_US |
dc.date.accessioned | 2014-12-08T15:46:21Z | - |
dc.date.available | 2014-12-08T15:46:21Z | - |
dc.date.issued | 2008 | en_US |
dc.identifier.isbn | 978-1-4244-2078-0 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/31187 | - |
dc.description.abstract | In this paper, a 32-bit reconfigurable multiplication-accumulation architecture, which can execute flexibly one 32x32, two 16x16 or four 8x8 two's complement multiply-accumulation, is proposed and demonstrated. It is based on the modified Booth encoding scheme and designed with techniques of reducing sign-extension bits, removing one extra partial product row and adjusting the positions of hot signals but with elegant modifications. It is implemented with a 130nm mixed-V(t) CMOS standard cell library and shows saving of area and power consumption by approximately 16% and 14% respectively as compared to the previous design. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A reconfigurable MAC architecture implemented with mixed-V(t) standard cell library | en_US |
dc.type | Article | en_US |
dc.identifier.journal | PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 | en_US |
dc.citation.spage | 3426 | en_US |
dc.citation.epage | 3429 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000258532102315 | - |
Appears in Collections: | Conferences Paper |