Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chang, GJ | en_US |
dc.contributor.author | Hwang, FK | en_US |
dc.contributor.author | Tong, LD | en_US |
dc.date.accessioned | 2014-12-08T15:46:24Z | - |
dc.date.available | 2014-12-08T15:46:24Z | - |
dc.date.issued | 1999-07-01 | en_US |
dc.identifier.issn | 0028-3045 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/31233 | - |
dc.description.abstract | In recent years, many multistage interconnection networks using 2 x 2 switching elements have been proposed for parallel architectures. Typical examples are baseline networks, banyan networks, shuffle-exchange networks, and their inverses. As these networks are blocking, such networks with extra stages have also been studied extensively. These include Benes networks and Delta + Delta' networks. Recently, Hwang et al, studied k-extra-stage networks, which are a generalization of the above networks. They also investigated the equivalence issue among some of these networks. In this paper, we studied a more general class of networks, which we call (m + 1)-stage d-nary bit permutation networks. We characterize the equivalence of such networks by sequence of positive integers. (C) 1999 John Wiley & Sons, Inc. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | multistage interconnection network | en_US |
dc.subject | switching network | en_US |
dc.subject | permutation routing | en_US |
dc.subject | Sterling number | en_US |
dc.subject | rearrangeably nonblocking | en_US |
dc.title | Characterizing bit permutation networks | en_US |
dc.type | Article | en_US |
dc.identifier.journal | NETWORKS | en_US |
dc.citation.volume | 33 | en_US |
dc.citation.issue | 4 | en_US |
dc.citation.spage | 261 | en_US |
dc.citation.epage | 267 | en_US |
dc.contributor.department | 應用數學系 | zh_TW |
dc.contributor.department | Department of Applied Mathematics | en_US |
dc.identifier.wosnumber | WOS:000081128200003 | - |
dc.citation.woscount | 11 | - |
Appears in Collections: | Articles |
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