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dc.contributor.authorWu, YHen_US
dc.contributor.authorChen, WJen_US
dc.contributor.authorChang, SLen_US
dc.contributor.authorChin, Aen_US
dc.contributor.authorGwo, Sen_US
dc.contributor.authorTsai, Cen_US
dc.date.accessioned2014-12-08T15:46:38Z-
dc.date.available2014-12-08T15:46:38Z-
dc.date.issued1999-05-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/55.761014en_US
dc.identifier.urihttp://hdl.handle.net/11536/31365-
dc.description.abstractWe have developed a simple process to form epitaxial CoSi2 for shallow junction. Prior to metal deposition, the patterned wafers were treated with HF-vapor passivation. As observed by scanning tunneling microscopy (STM), this HF, treatment drastically improves the native oxide-induced sur face roughness. The epitaxial behavior was confirmed by cross-sectional transmission electron microscopy (TEM), Decreased sheet resistance and leakage current, and improved thermal stability are displayed by the HF treated samples, which is consistent with STM and TEM results.en_US
dc.language.isoen_USen_US
dc.subjectepitaxial CoSi2en_US
dc.subjectHF pretreatmenten_US
dc.titleImproved electrical characteristics of CoSi2 using HF-vapor pretreatmenten_US
dc.typeArticleen_US
dc.identifier.doi10.1109/55.761014en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume20en_US
dc.citation.issue5en_US
dc.citation.spage200en_US
dc.citation.epage202en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000081151400003-
dc.citation.woscount2-
Appears in Collections:Articles


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