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dc.contributor.authorTseng, WDen_US
dc.contributor.authorWang, KCen_US
dc.date.accessioned2014-12-08T15:46:51Z-
dc.date.available2014-12-08T15:46:51Z-
dc.date.issued1999-03-01en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://dx.doi.org/10.1109/92.748207en_US
dc.identifier.urihttp://hdl.handle.net/11536/31495-
dc.description.abstractWe propose a fuzzy-based approach which pro,ides a soft threshold to determine the module size for CMOS circuit partitioning in built-in current testing (BICT). Experimental results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning in comparison with other approaches with a fixed threshold, and a better module size can thus he determined to reflect a change of circuit properties.en_US
dc.language.isoen_USen_US
dc.subjectCMOSen_US
dc.subjectcosten_US
dc.subjectpartitioningen_US
dc.subjectperformanceen_US
dc.subjecttesten_US
dc.titleFuzzy-based CMOS circuit partitioning in built-in current testingen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/92.748207en_US
dc.identifier.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSen_US
dc.citation.volume7en_US
dc.citation.issue1en_US
dc.citation.spage116en_US
dc.citation.epage120en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000078920900013-
dc.citation.woscount0-
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