標題: | Fuzzy-based CMOS circuit partitioning in built-in current testing |
作者: | Tseng, WD Wang, KC 資訊工程學系 Department of Computer Science |
關鍵字: | CMOS;cost;partitioning;performance;test |
公開日期: | 1-三月-1999 |
摘要: | We propose a fuzzy-based approach which pro,ides a soft threshold to determine the module size for CMOS circuit partitioning in built-in current testing (BICT). Experimental results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning in comparison with other approaches with a fixed threshold, and a better module size can thus he determined to reflect a change of circuit properties. |
URI: | http://dx.doi.org/10.1109/92.748207 http://hdl.handle.net/11536/31495 |
ISSN: | 1063-8210 |
DOI: | 10.1109/92.748207 |
期刊: | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
Volume: | 7 |
Issue: | 1 |
起始頁: | 116 |
結束頁: | 120 |
顯示於類別: | 期刊論文 |