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dc.contributor.authorCYPHER, Ren_US
dc.contributor.authorSHUNG, CBen_US
dc.date.accessioned2014-12-08T15:04:40Z-
dc.date.available2014-12-08T15:04:40Z-
dc.date.issued1993-01-01en_US
dc.identifier.issn0922-5773en_US
dc.identifier.urihttp://dx.doi.org/10.1007/BF01880274en_US
dc.identifier.urihttp://hdl.handle.net/11536/3155-
dc.description.abstractThe trace-back technique is an effective approach for survivor memory management in the Viterbi algorithm. It is especially attractive when the number of states in the trellis is large, in which case the register exchange approach is impractical due to the area required for wiring. Previous descriptions of the trace-back technique have assumed either one or two trace-back pointers and have made specific assumptions about the speeds of those pointers. In this paper we present a general framework for implementing the trace-back technique with any number of traceback pointers and with relaxed assumptions about the speeds of the pointers. We also show that the use of additional trace-back pointers reduces the memory requirements. Two implementations of the generalized trace-back techniques based on standard RAMs and custom shift registers are presented.en_US
dc.language.isoen_USen_US
dc.subjectVITERBI ALGORITHMen_US
dc.subjectTRACE-BACKen_US
dc.subjectSURVIVOR MEMORYen_US
dc.subjectVLSI AREA REQUIREMENTSen_US
dc.titleGENERALIZED TRACE-BACK TECHNIQUES FOR SURVIVOR MEMORY MANAGEMENT IN THE VITERBI ALGORITHMen_US
dc.typeArticleen_US
dc.identifier.doi10.1007/BF01880274en_US
dc.identifier.journalJOURNAL OF VLSI SIGNAL PROCESSINGen_US
dc.citation.volume5en_US
dc.citation.issue1en_US
dc.citation.spage85en_US
dc.citation.epage94en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:A1993KT58400008-
dc.citation.woscount23-
Appears in Collections:Articles