A NEW ARRAY ARCHITECTURE FOR PRIME-LENGTH DISCRETE COSINE TRANSFORM

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	GUO, JI	en_US
dc.contributor.author	LIU, CM	en_US
dc.contributor.author	JEN, CW	en_US
dc.date.accessioned	2014-12-08T15:04:40Z	-
dc.date.available	2014-12-08T15:04:40Z	-
dc.date.issued	1993-01-01	en_US
dc.identifier.issn	1053-587X	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/TSP.1993.193173	en_US
dc.identifier.uri	http://hdl.handle.net/11536/3159	-
dc.description.abstract	A new approach to derive a systolic algorithm for prime-length discrete cosine transform (DCT) is proposed. It makes use of the input/output (I/O) data permutations and the symmetry property of cosine kernels such that the proposed array possesses outstanding performance in hardware cost of the processing elements (PE's), average computation time, and the I/O cost.	en_US
dc.language.iso	en_US	en_US
dc.title	A NEW ARRAY ARCHITECTURE FOR PRIME-LENGTH DISCRETE COSINE TRANSFORM	en_US
dc.type	Letter	en_US
dc.identifier.doi	10.1109/TSP.1993.193173	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON SIGNAL PROCESSING	en_US
dc.citation.volume	41	en_US
dc.citation.issue	1	en_US
dc.citation.spage	436	en_US
dc.citation.epage	442	en_US
dc.contributor.department	資訊工程學系	zh_TW
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Computer Science	en_US
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1993KG14800046	-
dc.citation.woscount	35	-
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