標題: A New VLSI 2-D Diagonal-Symmetry Filter Architecture Design
作者: Chen, Pei-Yu
Van, Lan-Da
Reddy, Hari C.
Lin, Chin-Teng
資訊工程學系
Department of Computer Science
公開日期: 2008
摘要: In this paper, we propose two new two-dimensional (2-D) IIR and FIR filter architectures for 2-D transfer function with diagonal symmetry. The presented type-I structure with diagonal symmetry has the lowest number of multipliers, and zero latency without sacrificing the number of the delay elements. Importantly, the proposed type-II IIR filter possesses high speed, local broadcast, and the same number of multipliers and latency as the type I shows at expense of a slight increment of number of delay elements.
URI: http://hdl.handle.net/11536/31809
ISBN: 978-1-4244-2341-5
期刊: 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4
起始頁: 320
結束頁: 323
顯示於類別:會議論文