標題: Effects of CoSi2 on p(+) polysilicon gates fabricated by BF2+ implantation into CoSi amorphous Si bilayers
作者: Cheng, HC
Lai, WK
Liu, HW
Juang, MH
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-十月-1998
摘要: The integrity of thin gate oxide structures fabricated by implanting BF2+ ions into bilayered CoSi/amorphous silicon films and subsequent annealing has been studied as a function of cobalt silicide thickness and implantation energy. Significant degradation of gate oxide integrity and flatband voltage shifts were found with increasing cobalt silicide thickness and annealing temperature. It is shown that although thinner cobalt silicide can result in excellent gate dielectric integrity it also leads to worse thermal stability at a high annealing temperature. Moreover, shallower implantation depth and lower annealing temperature can reduce the boron penetration, but depletion effects in polycrystalline silicon gates are caused accordingly. Hence, appropriate process conditions, involving trade-offs among CoSi2 thickness, implantation energy and annealing temperature, must be used to optimize the device performance while retaining the thin dielectric reliability.
URI: http://hdl.handle.net/11536/31861
ISSN: 0013-4651
期刊: JOURNAL OF THE ELECTROCHEMICAL SOCIETY
Volume: 145
Issue: 10
起始頁: 3590
結束頁: 3594
顯示於類別:期刊論文


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