完整後設資料紀錄
DC 欄位語言
dc.contributor.authorCheng, HCen_US
dc.contributor.authorLai, WKen_US
dc.contributor.authorLiu, HWen_US
dc.contributor.authorJuang, MHen_US
dc.date.accessioned2014-12-08T15:47:36Z-
dc.date.available2014-12-08T15:47:36Z-
dc.date.issued1998-10-01en_US
dc.identifier.issn0013-4651en_US
dc.identifier.urihttp://hdl.handle.net/11536/31861-
dc.description.abstractThe integrity of thin gate oxide structures fabricated by implanting BF2+ ions into bilayered CoSi/amorphous silicon films and subsequent annealing has been studied as a function of cobalt silicide thickness and implantation energy. Significant degradation of gate oxide integrity and flatband voltage shifts were found with increasing cobalt silicide thickness and annealing temperature. It is shown that although thinner cobalt silicide can result in excellent gate dielectric integrity it also leads to worse thermal stability at a high annealing temperature. Moreover, shallower implantation depth and lower annealing temperature can reduce the boron penetration, but depletion effects in polycrystalline silicon gates are caused accordingly. Hence, appropriate process conditions, involving trade-offs among CoSi2 thickness, implantation energy and annealing temperature, must be used to optimize the device performance while retaining the thin dielectric reliability.en_US
dc.language.isoen_USen_US
dc.titleEffects of CoSi2 on p(+) polysilicon gates fabricated by BF2+ implantation into CoSi amorphous Si bilayersen_US
dc.typeArticleen_US
dc.identifier.journalJOURNAL OF THE ELECTROCHEMICAL SOCIETYen_US
dc.citation.volume145en_US
dc.citation.issue10en_US
dc.citation.spage3590en_US
dc.citation.epage3594en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000076217000043-
dc.citation.woscount0-
顯示於類別:期刊論文


文件中的檔案:

  1. 000076217000043.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。