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dc.contributor.authorCHOU, HCen_US
dc.contributor.authorCHUNG, CPen_US
dc.date.accessioned2014-12-08T15:04:42Z-
dc.date.available2014-12-08T15:04:42Z-
dc.date.issued1993en_US
dc.identifier.issn0006-3835en_US
dc.identifier.urihttp://hdl.handle.net/11536/3191-
dc.identifier.urihttp://dx.doi.org/10.1007/BF01990519en_US
dc.description.abstractThe problem of superscalar instruction scheduling is studied and an analysis of a heuristic scheduling algorithm is presented. First, a superscalar architecture is characterized by k, the number of types of functional units employed, m(i), the number of type i functional units, P(ij), the jth functional unit of type i, and z, the maximal number of delay cycles incurred by the execution of instructions. A program trace to be scheduled is modeled by a directed acyclic graph with delay on precedence relations. These two models reflect most of the flavor of the superscalar instruction scheduling problem. A heuristic scheduling algorithm called the ECG-algorithm is designed by compiling two scheduling guidelines. The performance of the ECG-algorithm is evaluated through worst-case analysis. Letting w(ECG) denote the length of an ECG-schedule and w(opt) the length of an optimal schedule, we established the bound w(ECG)/w(opt) less-than-or-equal-to k + 1 - 2/[max {m(i)}(z + 1)], which is smaller than other known bounds.en_US
dc.language.isoen_USen_US
dc.subjectSCHEDULINGen_US
dc.subjectPARALLEL PROCESSINGen_US
dc.subjectHEURISTIC METHODSen_US
dc.subjectWORST-CASE ANALYSISen_US
dc.titleMODELING OF SUPERSCALAR INSTRUCTION SCHEDULING AND ANALYSIS OF A HEURISTIC SCHEDULING ALGORITHMen_US
dc.typeArticleen_US
dc.identifier.doi10.1007/BF01990519en_US
dc.identifier.journalBITen_US
dc.citation.volume33en_US
dc.citation.issue3en_US
dc.citation.spage354en_US
dc.citation.epage371en_US
dc.contributor.department資訊科學與工程研究所zh_TW
dc.contributor.departmentInstitute of Computer Science and Engineeringen_US
dc.identifier.wosnumberWOS:A1993LZ68700001-
dc.citation.woscount0-
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