Title: | Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection |
Authors: | Yeh, Chih-Ting Ker, Ming-Dou 電機學院 College of Electrical and Computer Engineering |
Keywords: | Big field-effect transistor (BigFET);electrostatic discharge (ESD);holding voltage;power-rail ESD clamp circuit |
Issue Date: | 1-Nov-2010 |
Abstract: | The RC-based power-rail ESD clamp circuit with the n-channel metal-oxide-semiconductor (NMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based ESD-transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions. |
URI: | http://dx.doi.org/10.1109/JSSC.2010.2075370 http://hdl.handle.net/11536/32011 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2010.2075370 |
Journal: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 45 |
Issue: | 11 |
Begin Page: | 2476 |
End Page: | 2486 |
Appears in Collections: | Articles |
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