In-Plane Gate Transistors Fabricated by Using Atomic Force Microscopy Anode Oxidation

doi:10.1109/LED.2010.2068273

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chung, Tung-Hsun	en_US
dc.contributor.author	Chen, Shu-Han	en_US
dc.contributor.author	Liao, Wen-Hsuan	en_US
dc.contributor.author	Lin, Shih-Yen	en_US
dc.date.accessioned	2014-12-08T15:47:59Z	-
dc.date.available	2014-12-08T15:47:59Z	-
dc.date.issued	2010-11-01	en_US
dc.identifier.issn	0741-3106	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/LED.2010.2068273	en_US
dc.identifier.uri	http://hdl.handle.net/11536/32030	-
dc.description.abstract	An in-plane gate transistor fabricated by using the atomic force microscopy (AFM) lithography is investigated in this letter. By performing repeated oxidation and deoxidation procedures by using the AFM for four times, two V-shaped trenches are fabricated on the prepatterned mesas to isolate the electrical terminals of the device. Without exposing the channel region to the atmosphere, the device has exhibited standard transistor current-voltage characteristics in the 0-5 V range at room temperature, which may be advantageous for the future high-speed application of the device.	en_US
dc.language.iso	en_US	en_US
dc.subject	Atomic force microscopy (AFM)	en_US
dc.subject	in-plane gate transistors	en_US
dc.title	In-Plane Gate Transistors Fabricated by Using Atomic Force Microscopy Anode Oxidation	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/LED.2010.2068273	en_US
dc.identifier.journal	IEEE ELECTRON DEVICE LETTERS	en_US
dc.citation.volume	31	en_US
dc.citation.issue	11	en_US
dc.citation.spage	1227	en_US
dc.citation.epage	1229	en_US
dc.contributor.department	光電工程學系	zh_TW
dc.contributor.department	Department of Photonics	en_US
dc.identifier.wosnumber	WOS:000283448300018	-
dc.citation.woscount	7	-
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