完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liang, C-P. | en_US |
dc.contributor.author | Huang, C-W. | en_US |
dc.contributor.author | Lin, Y-K. | en_US |
dc.contributor.author | Chung, S-J. | en_US |
dc.date.accessioned | 2014-12-08T15:48:34Z | - |
dc.date.available | 2014-12-08T15:48:34Z | - |
dc.date.issued | 2010-08-05 | en_US |
dc.identifier.issn | 0013-5194 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1049/el.2010.1279 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/32307 | - |
dc.description.abstract | A low-power and low-noise amplifier with a new input-matching technique using 0.18 mu m CMOS technology for ultra-wideband applications is presented. A proposed broadband input match can be acquired easily by selecting an appropriate width of the transistor, which will effectively avoid the usage of the low-Q on-chip inductors in the input network. Moreover, demonstrated is the feasibility of the inter-stage resonator to accomplish bandwidth enhancement without additional power consumption. The IC prototype achieves good performances such as a power gain of 16.2 dB, a better than 10 dB input return loss, and 2.3 dB minimum noise figure while consuming a DC core power of only 6.8 mW. | en_US |
dc.language.iso | en_US | en_US |
dc.title | 3-10 GHz ultra-wideband low-noise amplifier with new matching technique | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1049/el.2010.1279 | en_US |
dc.identifier.journal | ELECTRONICS LETTERS | en_US |
dc.citation.volume | 46 | en_US |
dc.citation.issue | 16 | en_US |
dc.citation.spage | 1102 | en_US |
dc.citation.epage | U18 | en_US |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.identifier.wosnumber | WOS:000280653700006 | - |
dc.citation.woscount | 0 | - |
顯示於類別: | 期刊論文 |