Improved output ESD protection by dynamic gate floating design

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DC Field	Value	Language
dc.contributor.author	Chang, HH	en_US
dc.contributor.author	Ker, MD	en_US
dc.date.accessioned	2014-12-08T15:48:43Z	-
dc.date.available	2014-12-08T15:48:43Z	-
dc.date.issued	1998-09-01	en_US
dc.identifier.issn	0018-9383	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/16.711378	en_US
dc.identifier.uri	http://hdl.handle.net/11536/32400	-
dc.description.abstract	A dynamic gate Boating design is proposed to improve ESD robustness of the CMOS output buffers with small drive capability. By using this novel design, the human-body-model (machine-model) ESD failure threshold of a 2-mA CMOS output buffer has been practically improved from 1 KV (100 V) to greater than 8 KV (1500 V) in a 0.35-mu m CMOS process.	en_US
dc.language.iso	en_US	en_US
dc.subject	ESD	en_US
dc.subject	ESD protection	en_US
dc.subject	output buffer	en_US
dc.title	Improved output ESD protection by dynamic gate floating design	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/16.711378	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON ELECTRON DEVICES	en_US
dc.citation.volume	45	en_US
dc.citation.issue	9	en_US
dc.citation.spage	2076	en_US
dc.citation.epage	2078	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000075486100031	-
dc.citation.woscount	5	-
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