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dc.contributor.authorLee, LSen_US
dc.contributor.authorLee, CLen_US
dc.date.accessioned2014-12-08T15:48:47Z-
dc.date.available2014-12-08T15:48:47Z-
dc.date.issued1998-08-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/16.704373en_US
dc.identifier.urihttp://hdl.handle.net/11536/32462-
dc.description.abstractIn this paper, a technique to use Ar ion-implantation on the p(+)a-Si or poly-Si gate to suppress the boron penetration in p(+) pMOSFET is proposed and demonstrated. An Ar-implantation of a dose over 5 x 10(15) cm(-2) is shown to be able to sustain 900 degrees C annealing for 30 min for the gate without having the underlying gate oxide quality degraded, It is believed to be due to gettering of fluorine, then consequently boron, by the bubble-like defects created by the Ar implantation in the p+ gate region to reduce the B penetration. Excellent electrical characteristics like dielectric breakdown (E-bd), interface state density (D-it), and charge-to-breakdown (Q(bd)) On the gate oxide are obtained. The technique is compatible to the present CMOS process. The submicron pMOSFET fabricated by applying this technique exhibit better subthreshold characteristics and hot carrier immunity.en_US
dc.language.isoen_USen_US
dc.subjectAr implantationen_US
dc.subjectboron penetrationen_US
dc.subjectp(+) pMOSFETen_US
dc.titleArgon ion-implantation on polysilicon or amorphous-silicon for boron penetration suppression in p(+) pMOSFETen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/16.704373en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume45en_US
dc.citation.issue8en_US
dc.citation.spage1737en_US
dc.citation.epage1744en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000074867000016-
dc.citation.woscount9-
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