完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, PY | en_US |
dc.contributor.author | Tsay, JC | en_US |
dc.date.accessioned | 2014-12-08T15:49:22Z | - |
dc.date.available | 2014-12-08T15:49:22Z | - |
dc.date.issued | 1998-02-01 | en_US |
dc.identifier.issn | 0018-9340 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/12.663767 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/32812 | - |
dc.description.abstract | The purpose of this paper is to describe a new method to design unidirectional modular extensible linear arrays far regular algorithms. The time complexity of our method is polynomial and depends only on the number of dimensions of the regular algorithm. The designed linear array is asymptotically optimal in space and time. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | algorithm transformation | en_US |
dc.subject | conflict-free mapping | en_US |
dc.subject | data dependency | en_US |
dc.subject | linear array | en_US |
dc.subject | modular extensible | en_US |
dc.subject | optimal spacetime mapping | en_US |
dc.subject | regular algorithm | en_US |
dc.subject | systolic array | en_US |
dc.subject | unimodular matrix | en_US |
dc.subject | VLSI | en_US |
dc.title | An approach to designing modular extensible linear arrays for regular algorithms | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/12.663767 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON COMPUTERS | en_US |
dc.citation.volume | 47 | en_US |
dc.citation.issue | 2 | en_US |
dc.citation.spage | 212 | en_US |
dc.citation.epage | 216 | en_US |
dc.contributor.department | 工學院 | zh_TW |
dc.contributor.department | College of Engineering | en_US |
dc.identifier.wosnumber | WOS:000072282100008 | - |
dc.citation.woscount | 0 | - |
顯示於類別: | 期刊論文 |