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dc.contributor.authorHSIAO, PYen_US
dc.contributor.authorYAN, JTen_US
dc.date.accessioned2014-12-08T15:04:51Z-
dc.date.available2014-12-08T15:04:51Z-
dc.date.issued1992-07-01en_US
dc.identifier.issn0143-7062en_US
dc.identifier.urihttp://hdl.handle.net/11536/3372-
dc.description.abstractAn efficient real time VLSI-CAD tool, the complementary design rule checker (CDRC), composed of one interactive phase and one batch phase is presented. It is a general geometrical design rule model which checks some of the layout constraints in the interative phase and the other constraints in the batch phase. Those classified constraints are disjointed, and each one of them should be checked only once either during the interactive or batch phase. This system and the embedded layout editor are designed on the basis of the binary balanced quad list quad tree (BBQLQT) and its region query functions. The BBQLQT is more efficient than the most recently published spatial data structure, the Weyten's quad list quad tree. One day, provided that the BBQLQT has being further improved, the performance of our system will be promoted without giving more additional design effort. This system is therefore proven to be fully modularised and independent of any of the other spatial data structures.en_US
dc.language.isoen_USen_US
dc.subjectCOMPUTER-AIDED DESIGNen_US
dc.subjectDESIGN RULE CHECKERen_US
dc.subjectVLSI LAYOUTen_US
dc.subjectBALANCED QUAD TREEen_US
dc.titleDESIGNING A COMPLEMENTARY DESIGN RULE CHECKER BASED ON A BINARY BALANCED QUAD LIST QUAD TREEen_US
dc.typeArticleen_US
dc.identifier.journalIEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUESen_US
dc.citation.volume139en_US
dc.citation.issue4en_US
dc.citation.spage311en_US
dc.citation.epage322en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:A1992JJ05100003-
dc.citation.woscount1-
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