一個關於先進製程技術關鍵區域分析工具之實作

Abstract

在本論文中，對於光罩佈局中的整合電路，我們提出一個針對短路錯誤的計算關鍵區域的方法。這個方法是利用取樣架構與關鍵區域的幾何計算的概念。藉由建立一個記錄密度表，我們加權的取樣方法可以讓結果更為準確且更適合較大的設計。這個演算法被建立在一個開放存取的平台上並且可以有效地從任意的佈局中萃取出關鍵區域。結果顯示，這個方法可以降低計算成本；同時，也可以保持準確性。

In this thesis, we present a method of computing critical area for short faults of an integrated circuit from the mask layout. The method is based on the concept of sampling framework and the geometry computation of critical area. By constructing the density table of layout, our weighted sampling approach can be more accurate and more suitable for the larger device. The algorithm has been implemented within OpenAccess platform to allow efficient extraction of the critical area from an arbitrary mask layout. The results show that this method can reduce computation cost; meanwhile, it can maintain the accuracy.