低溫複晶矽薄膜電晶體在閘極關閉區脈衝電壓及汲極直流偏壓下的劣化研究

Abstract

低溫複晶矽薄膜電晶體 (poly-Si TFTs) 與非晶矽薄膜電晶體 (a-Si TFTs) 相比，具有較高的驅動電流，這是因爲電子在複晶矽的傳輸速度較快、膜品質也較優良，因而可以使薄膜電晶體的尺寸更小，並增加顯示器的亮度及減少功率消耗。另外，低溫多晶矽薄膜電晶體可在玻璃基板上嵌入驅動元件，並且大幅減少驅動IC的空間，更提升液晶顯示面板的特性及可靠度，使面板的製造成本降低，因此它的發展將使顯示系統可以整合在玻璃基板上。然而，TFT在系統面板中的電路之操作是多樣而動態的；因此，為了保證產品的壽命，TFT在這些操作條件的可靠度必須加以探討。 在這篇論文中，我們排除了overshooting的效應，進一步研究了低溫複晶矽薄膜電晶體在閘極 (gate) 關閉區脈衝電壓、及不同汲極 (drain) 直流偏壓下的劣化情形。對N-type TFTs而言，當閘極電壓是在 ±15V內操作、且源極 (source) 和汲極端接地時，元件的劣化只會和閘極脈波下降的時間有關，和上升的時間不相關；但是如果閘極交流電壓的操作範圍小於臨界電壓、又源極和汲極端接地時，元件的劣化會同時和閘極脈波上升及下降的時間有關。對P-type TFTs而言，則是和N-type TFTs劣化情形不同，當閘極電壓是在 ±15V內操作、且源極和汲極端接地時，元件的劣化只會和閘極脈波上升的時間有關，和下降的時間不相關；但是如果閘極電壓的範圍是從0V掃到15V、又源極和汲極端接地時，元件的劣化會和閘極脈波上升及下降的時間皆不相關。 且根據實驗結果發現，對N-type和P-type在閘極關閉區脈衝電壓、汲極端加偏壓的情形，劣化會隨著汲極端偏壓的加大而更趨嚴重，且源極和汲極會產生不同的劣化行為。然而，P-type不論在電流－電壓、還是電容－電壓曲線的劣化，都不如N-type明顯。同時元件的劣化也會和閘極電壓的範圍有關，而閘極電壓的上升時間和下降時間效應，因為汲極端的偏壓會產生其他影響，使得上升時間和下降時間的效應不明顯。

The driving current of panel of low temperature polycrystalline silicon thin film transistors (LTPS TFTs) is higher than the amorphous silicon thin film transistors (a-Si TFTs). The fast mobility in the good film of LTPS TFTs can make the size of TFTs small. Therefore, the display luminance can be increased and power consumption can be reduced. Furthermore, LTPS TFTs can be used to implement active circuits on single glass substrates and diminish spaces of active IC. It not only promotes the characteristic and reliability in liquid crystal display, but also comes down the manufacturing cost. So, it makes display systems with integrated circuit on the glass substrates to be feasible. However, the operation of the TFTs in the circuit of display system can be diverse and dynamic. Therefore, to insure the lifetime of the product, the reliability of TFTs under such kinds of operation conditions must be studied. In this thesis, the device degradation of low-temperature polycrystalline thin film transistor under gate AC stress in off region with different drain bias has been investigated where the overshooting effect is prevented. For the N-type TFTs under the stress of gate voltage swinging from -15V to 15V with source and drain grounded, the device degradation depends on the falling time of gate pulse, but not on the rising time. However, under the stress of gate voltage lower than the threshold voltage, the degradation is dependent on both the rising time and falling time of the gate signal. For the P-type TFTs under the stress of gate voltage swinging from -15V to 15V with source and drain grounded, the device degradation depends on the rising time of gate pulse, but not on falling time. However, under the stress of gate voltage swinging from 0V to 15V, the degradation is independent of the rising time and falling time. For the N-type and P-type TFTs under gate AC stress in off region with drain bias, the degradation becomes worse with increasing drain voltage. It results in different degradation behaviors near the source and drain regions. The I-V and C-V characteristic of P-type TFTs are not that much degraded than those of N-type TFTs. With the increase of the range of gate pulse, the degradation also increases. The applied drain voltage may introduce the effects of large electric field near the drain. In contrast, the effects of rising time and falling time are not obvious.