完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 劉大偉 | en_US |
dc.contributor.author | Liu Ta Wei | en_US |
dc.contributor.author | 林鴻志 | en_US |
dc.contributor.author | 黃調元 | en_US |
dc.contributor.author | Horng-Chih Lin | en_US |
dc.contributor.author | Tiao-Yuan Huang | en_US |
dc.date.accessioned | 2014-12-12T01:13:32Z | - |
dc.date.available | 2014-12-12T01:13:32Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT009511507 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/38052 | - |
dc.description.abstract | 在本篇論文中,我們利用簡單、低成本而且富變化性的方法製作數種具有相同奈米線型狀,但是不同閘極組態的複晶矽奈米線元件,這些元件有助於我們探討多閘極對於奈米線元件的基本電性和特性變異度的影響。相較於平面結構元件,實驗結果證明奈米線具有較好的次臨界擺幅(subthreshold swing)、較低的漏電流,以及較大的開關電流比(on/off current ratio)。我們實驗的數據也顯示,當奈米線的通道表面被閘極覆蓋的比例愈大時,由於具有較高的表面體積比(surface-to-volume ratio),會展現出更好的特性。我們也藉由臨界電壓(threshold voltage)的標準差和閘極寬度、長度乘積開根號( )的關係來探討不同元件之間特性的變異度,發現環繞全閘極(gate-all-around)結構的奈米線元件呈現出最穩定的臨界電壓控制能力,而平面元件由於有較大的空乏區以及較差的電漿修補效果,因此不同元件之間的臨界電壓差異性較大。 此外,我們也製作三閘極(tri-gate)奈米線結構的SONOS元件。相較於平面結構,奈米線元件的寫入和抹除速度有很明顯的改善;在可靠度議題方面,奈米線元件擁有不錯的電荷儲存能力(retention)和忍耐力(endurance),它可以承受超過10000次的重複寫入/抹除,並且在十年後仍然維持大於0.5V的記憶窗(memory window)。 | zh_TW |
dc.description.abstract | In this thesis, several multiple-gated (MG) poly-Si nanowire (NW) devices were fabricated and characterized. Our fabrication process is simple, low cot, and flexible for fabricating devices with identical NW structure but different gate configuration. It thus allows us to investigate the impacts of MG on the basic electrical characteristics as well as the variation of devices. The experimental results show that, as compared with devices with planar structure, much improved device characteristics in terms of better subthreshold swing, lower leakage, and higher on/off ratio are obtained. Among all NW structures, superior device performance is achieved as the gated portion of NW channel surface increases, owing to the higher surface-to-volume ratio. We also study the device variation issue by plotting the standard deviation of VTH as a function of . We found that the device with gate-all-around configuration exhibits the best control in terms of the variation. Besides, the deviation of planar devices is evidently higher than the NW ones because of wider depletion width and worse plasma treatment efficiency. Tri-gated SONOS devices were also fabricated and characterized with a process flow modified from the aforementioned one. It is confirmed that the NW devices have higher P/E speed than planar ones. For reliability issue, NW SONOS devices possess good retention and endurance characteristics. The memory window is larger than 0.5V after 10 years for a device after subjecting to 104 times of P/E cycles. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 表面體積比 | zh_TW |
dc.subject | 環繞全閘極 | zh_TW |
dc.subject | 電荷儲存能力 | zh_TW |
dc.subject | 忍耐力 | zh_TW |
dc.subject | 記憶窗 | zh_TW |
dc.subject | surface-to-volume ratio | en_US |
dc.subject | gate-all-around | en_US |
dc.subject | retention | en_US |
dc.subject | endurance | en_US |
dc.subject | memory window | en_US |
dc.title | 新式複晶矽奈米線元件製作與特性分析 | zh_TW |
dc.title | Fabrication and Characterization of Novel Poly-Si Nanowire Devices | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |