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dc.contributor.author趙元鵬en_US
dc.contributor.authorYuan-Peng Chaoen_US
dc.contributor.author汪大暉en_US
dc.contributor.authorTahui Wangen_US
dc.date.accessioned2014-12-12T01:13:34Z-
dc.date.available2014-12-12T01:13:34Z-
dc.date.issued2007en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009511521en_US
dc.identifier.urihttp://hdl.handle.net/11536/38063-
dc.description.abstract本篇論文主要提供了一個新的方法來探測小面積SONOS快閃記憶體沿著通道的表面電位變化,這個新方法是藉由結合缺陷位置萃取技術和底層二氧化矽缺陷所產生的隨機電報雜訊(Random Telegraph Noise)來達成。 我們使用這個新方法來驗證SONOS快閃記憶體中通道熱電子(Channel Hot Electron)的寫入電荷分佈和通道引發二次電子射入的電荷分佈之不同。此外,這個方法也被應用在觀察通道熱電子寫入和能帶到能帶穿隧產生之熱電動(Band-to-Band Tunneling Hot Hole)抹除電荷分佈的不對稱現象。最後,高溫下氮化矽中的正電荷遷移也有利用此方法研究。zh_TW
dc.description.abstractThe main concept of this dissertation provides a new method to probe the change of the surface potential along the channel in a small area SONOS type memory. It is accomplished by combining the extraction of the trap position with the random telegraph signal (RTS) resulted from the interface trap located in the bottom oxide. This method is used to verify the difference of the program charge distribution between channel hot electron (CHE) and channel initiated secondary electron (CHISEL) injection. Moreover, this method could be applied to observe the charge misalignment of CHE program and band-to-band tunneling (BTBT) hot hole erase. The migration of the positive charge in the nitride layer is also inspected as well.en_US
dc.language.isoen_USen_US
dc.subject氮化矽zh_TW
dc.subject隨機電報訊號zh_TW
dc.subjectSONOSen_US
dc.subjectRTSen_US
dc.title利用RTS 方法研究SONOS 快閃記憶體寫入/抹除電荷之橫向分佈特性zh_TW
dc.titleCharacterization of Program/Erase Charge Lateral Distribution in SONOS Flash Memory Cell by Using RTS Techniqueen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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