具環繞閘極與多重奈米通道之複晶矽薄膜電晶體研究

Abstract

複晶矽薄膜電晶體被廣泛的應用於主動式矩陣平面顯示器的開關元件，而為了要更進一步把複晶矽薄膜電晶體應用在系統面板和三維立體積體電路上，複晶矽薄膜電晶體的尺寸勢必要縮小來提高積體電路的密度和操作速度。然而當傳統複晶矽薄膜電晶體的尺寸縮小時，由於在通道中的晶界缺陷和薄膜電晶體的浮體結構(Floating Body)，元件會發生一些非理想的效應，像是臨界電壓下降、汲極誘導能障下降和紐結效應(Kink Effect)。在這篇論文裡我們提出了新穎具環繞閘極與多重奈米通道之複晶矽薄膜電晶體來改善元件的性能。 在第二章，我們利用一種簡單且低成本的方式來製作元件。我們利用間隙壁技術(Spacer Technique)來製作奈米通道而不用先進的微影技術。並利用蝕刻犧牲氧化層來讓奈米通道懸空能被閘極完全包覆形成環繞閘極結構。由掃描式電子顯微鏡和穿透式電子顯微鏡的觀察發現閘極與閘極氧化層的包覆非常的均勻。製作出的具環繞閘極與多重奈米通道之複晶矽薄膜電晶體和傳統的元件比較起來有相當良好的電特性。在電晶體導通時，我們的元件有較低的臨界電壓(由2.31到1.31 V)、較小的汲極誘導能障下降(由0.29到0.04 V/V)、較陡峭的次臨界擺幅(由0.64到0.37 V/decade)、較低的紐結電流、較高的導通電流(由 3.81×10-5到4.17×10-5 A)與載子移動率(由26到33 cm2/V-s)。當電晶體關閉，我們的元件在低閘極電壓時有較低的漏電流，但在高閘極電壓時有較高的漏電流，這是由於我們的元件有較高的閘極電場。 在第三章，我們更進一步的研究具環繞閘極與多重奈米通道之複晶矽薄膜電晶體的特性。在氨電漿鈍化效應上，我們的元件能更有效的被氨電漿鈍化。此外，我們比較了具環繞閘極與多重奈米通道、具斜邊閘極與多重奈米通道與傳統閘極三種不同結構的複晶矽薄膜電晶體。在這些結構中，具環繞閘極與奈米通道的複晶矽薄膜電晶體展現了最好的特性。另外我們也比較不同尺寸的元件，和傳統的複晶矽薄膜電晶體相比，我們的元件也能有效抑制短通道效應和窄通道效應。另一方面，我們應用間隙壁奈米通道的尖端成功製作場發射元件。

Poly-Si thin film transistors (TFTs) have been widely used as switching elements in active matrix displays. Further, for the applications on system-on-panel (SOP) and three-dimension integrated circuits (3-D ICs), scaled-down poly-Si TFTs are needed for higher integrated density and faster speed. However, there are some undesired effects in conventional scaled-down poly-Si TFTs such as threshold voltage (Vth) roll-off, drain-induced barrier lowering (DIBL), and kink effect which are caused from the grain boundary defects and the floating body in channel region. In this thesis, novel gate-all-around poly-Si TFTs with multiple nanowire channels (GAA-MNC TFTs) were proposed to improve the device performance. In the chapter 2, a simple and low-cost method was used in fabricating the GAA-MNC TFTs. The spacer technique was used to form the multiple nanowire channels without any advanced lithography. Moreover, the suspending nanowires after sacrificial oxide stripping were achieved to establish the gate-all-around structure. From the analyses of scanning electron microscope (SEM) and transmission electron microscope (TEM), good conformal depositions of gate-oxide and poly-gate thin films were clearly observed. The fabricated GAA-MNC TFTs exhibit excellent electrical performance as compared with conventional ones. Under the on-state operation, the GAA-MNC TFTs demonstrate lower Vth (from 2.31 to 1.31 V), smaller DIBL (from 0.29 to 0.04 V/V), stepper subthreshold swing (SS) (from 0.64 to 0.37 V/decade), less kink current, higher on current (from 3.81×10-5 to 4.17×10-5 A), and higher mobility (from 26 to 33 cm2/V-s). In the off-state region, the GAA-MNC TFTs show lower minimum leakage current at low gate voltage but higher leakage current at high gate voltage. It is because the higher gate electric field in the GAA-MNC TFTs. In the chapter 3, further electrical characterizations of GAA-MNC TFTs were studied in detail. On the plasma-passivation aspect, the GAA-MNC TFTs exhibit better defect passivation efficiency than conventional TFTs. Besides, TFTs with different gate structures, which are GAA-MNC, bevel-side-gate (BSG)-MNC, and conventional top-gate TFTs were designed and discussed. Among those, the GAA-MNC TFTs display the best performance. Moreover, the GAA-MNC and conventional TFTs with different dimensions were also discussed. The GAA-MNC TFTs demonstrate excellent immunity on the short-channel and narrow-width effects. On the other hand, the poly-Si spacer nanowires were successfully applied to make high electric field at those sharp corners to achieve field emission devices.