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dc.contributor.author張家銘en_US
dc.contributor.authorChia-Ming Changen_US
dc.contributor.author莊紹勳en_US
dc.contributor.authorSteve S. Chungen_US
dc.date.accessioned2014-12-12T01:13:49Z-
dc.date.available2014-12-12T01:13:49Z-
dc.date.issued2007en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009511574en_US
dc.identifier.urihttp://hdl.handle.net/11536/38106-
dc.description.abstract為了符合低功率的要求,閘極高介電材質的使用隨著閘級氧化層的微縮越來越有取代二氧化矽的趨勢。除了可以得到一樣的等效氧化層厚度之外,還可以明顯降低閘極漏電流超過三個數量級。但是高介電材質閘極有許多的可靠度問題,主要是來自於高介電閘極層中有許多缺陷抓取電荷,因此在實際電路操作時,會產生臨界電壓,汲極電流等的不穩定。 本論文中,將使用一個新的方法,稱作「閘極電流隨機電報訊號」方法來分析高介電材料閘極層中電荷抓取及放出的現象。透過給一固定的閘極電壓觀察閘極電流,閘極直接穿隧電流會在多個層次間振動,其原因來自於電荷在穿越閘極層時,會掉進閘極層裡面的缺陷並被抓住,但又容易藉著熱從缺陷中散逸。當電荷被抓取時會降低閘極穿隧電流,放出後電流又恢復,透過統計抓取及放出的時間,可以得到缺陷的特性,另外藉由觀察電流振幅了解在電路上的影響。 我們運用此方法來觀察三種不同的缺陷,包括製程產生的缺陷、元件經過不同電壓破壞之後產生的缺陷以及介電層在軟崩潰之後的影響。由此方法觀察到的閘極電流不穩定性可判斷出閘極介電層的劣化程度,不同程度的破壞會使電荷抓取及放出的機制受到影響。另外藉由改變溫度量測,可以更有效的了解此現象並且得知元件的可靠度。zh_TW
dc.description.abstractIn order to meet the requirement for low power circuit application, high-k gate dielectrics are being implemented in Si CMOS technologies with aggressive oxide thickness scaling. For the same EOT practical high-k gate dielectrics, one can provide significant reductions (>103) in the gate leakage. Reliability characteristics will be one of the primary goals of future development work, in which a large amount of traps in high-k bulk layer demonstrates the trapping and detrapping phenomena of carries. It causes the instability of threshold voltage, drain current, etc. In this thesis, a newly method, Gate Current Random Telegraph Noise, will be utilized to analyze the phenomenon of carriers trapping/detrapping in high-k gate dielectrics. We observe gate current by biasing the gate at fixed voltage and gate direct tunneling current will show two or three levels. The cause is carriers trapping in the trap site during tunneling through gate dielectrics and detrapping by thermal emission. Gate current is suppressed when traps capture carriers and recovers as traps empty. By statistically extracting capture and emission time, we can understand the trap properties. Besides, the influence will be understood by observing the variation of current fluctuation. We then apply this method to study three types of traps, including process induced traps, stress induced traps at distinct stress voltages, and post soft-breakdown character. Through the observation of gate current instability the degradation of gate dielectrics can be recognized. The experiment result shows the capture/emission mechanism affected by degrees of degradation. On the other hand, the appearance of gate current random telegraph noise is effectively investigated by measuring at different temperatures and the reliability of devices can be well understood.en_US
dc.language.isoen_USen_US
dc.subject高閘極介電層zh_TW
dc.subject隨機電報zh_TW
dc.subject閘極電流不穩定性zh_TW
dc.subject金氧半電晶體zh_TW
dc.subjectHigh-ken_US
dc.subjectRandom Telegraph Noiseen_US
dc.subjectGate Current Instabilityen_US
dc.subjectMOSFETen_US
dc.title探討高閘極介電層N通道金氧半電晶體的新穎閘極電流隨機電報量測法zh_TW
dc.titleThe Observation of Gate Current Instability in High-k Gate Dielectric MOSFET by a New Gate Current Random Telegraph Noise Approachen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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