鍺基板及磊晶鍺通道製作P型金氧半場效電晶體與電性分析研究

Abstract

我們已經成功地利用低溫的Forming Gas Anneal (FGA) 技術來改善以鍺為基板的金氧半場效電晶體。從電性的分析中，我們發現到在FGA 技術中300oC為較佳的條件，由於有最低的漏電流。然而在溫度超過300oC後，元件中的漏電流會明顯的上升，尤其是在溫度為400oC。我們認為是因為在接面附近產生缺陷所導致的。而缺陷的產生是因為鋁融進鍺基板和鍺在高溫會向外擴散所造成的。FGA 技術中300oC還有其他較好的特性。譬如說，有較好的閘集介電質和鍺基板的界面，所以導致有最低的界面態位密度 (interface state density)。由於，300oC有較低的漏電流，所以使得在這溫度之下的元件有較大的開關比。雖然300oC有上述等的優點，但是，它的載子遷移率卻相對400oC來說卻小的許多。我們認為是因為源集和汲集電阻所造成的。 經過400oC處理之後的元件，雖然會造成閘集介電質和鍺基板的界面退化使得界面態位密度變高。但是因為有最低的源集和汲集電阻所以導致有最高的電洞遷移率。為了要獲得這兩種溫度之下的好處，所以我們認為改變製程的順序或許是個解決的辦法。 接著為了有更好的界面特性以及大尺寸可應用於矽的製程中，我們使用以矽為基板，利用超高真空化學氣相沉積系統疊上矽鍺的緩衝層、鍺通道，以及不同厚度的矽的保護層。但是由於我們並沒有抓到較好的薄膜沉積條件，使得矽與鍺的接面並不理想，造成較高的接面漏電流。而且，我們也發現到矽保護層的厚度愈厚，電性的表現是愈差的。所以我們也認為較高的漏電流也有可能是因為在矽保護層內的雜質並不能被完全活化所引起的。所以我們認為要獲得更好的金氧半場效電晶體的特性，我們必須要找出更好的薄膜沉積條件以及必需把矽保護層的厚度降低到1奈米之下。

We had already employed low temperature Forming Gas Anneal (FGA) technique to improve the characteristics of Ge bulk p-MOSFETs. We found out the better temperature condition as 300oC FGA from the electric analysis, due to the lower OFF current. However, OFF current in devices obviously increased when the FGA temperature was over 300oC, especially in 400oC. We expected the cause of higher leakage current was the defects were generated near the p+-n junction region. The causes of generation of defects were Aluminum incorporated into Ge bulk and Ge out-diffusion in high temperature. 300oC FGA samples had other better characteristics. For example, it had the better interface quality between the Ge substrate and gate dielectric resulted in the lower interface state density in our works. Due to the lower OFF current in 300oC FGA samples, it had the larger ON/OFF ratio. Although, 300oC FGA samples had several advantages, the hole mobility is smaller than 400oC FGA samples. We though the cause of smaller mobility was the source/drain series resistance. Samples after 400oC FGA would degrade the interface quality between the Ge bulk and gate dielectric resulted in higher interface state density. But it had the lowest source/drain resistance led to the highest hole mobility in our works. In order to obtainment of the advantages in two different temperatures, we thought the change in process orders was a solution to solve this problem. In order to obtainment of better interface quality and application of larger size in Si process, we utilized ultra high vacuum chemical vapor deposition (UHVCVD) to deposit SiGe buffer layer, Ge channel, and Si capping layers top of Si substrate. But we didn’t obtain the better deposition conditions to deposit Ge and Si capping layer such that our p+-n junctions in this substrate were higher. However, we also found out the thicker Si capping layer would cause the poor characteristics in our samples. Hence, we also expected the higher leakage current was resulted in the implant impurities in Si capping layer were not completely removed. In order to obtainment of better characteristics in Ge p-MOSFETS, we must find out the better deposition conditions and reduce the thickness of Si capping layer down to 1 nm.