完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 曾友良 | en_US |
dc.contributor.author | Yu-Liang Tseng | en_US |
dc.contributor.author | 莊紹勳 | en_US |
dc.contributor.author | Steve S. Chung | en_US |
dc.date.accessioned | 2014-12-12T01:13:51Z | - |
dc.date.available | 2014-12-12T01:13:51Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT009511599 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/38128 | - |
dc.description.abstract | 當元件氧化層持續微縮時,以二氧化矽為基底做為 CMOS 元件因為閘極漏電流過高,無法滿足低功率電路的要求,故以高介電係數材料取代二氧化矽是一個重要的課題。近年來在研究氮氧化鉿矽上,指出可提高介電層物理厚度且有效降低閘極漏電流。與傳統的二氧化矽或氮氧化矽閘極氧化層相比,以鉿為材料的高介電常數閘極介電層具有相當嚴重的可靠度問題:臨界電壓漂移和操作電流的不穩定性,起因於高介電材料層中有大量的缺陷,導致電荷捕捉與逃逸現象。所以發展一套完整且可靠的方法去分析電荷捕捉的特性顯得相當重要。 本論文中,將以已發展成熟的「電荷幫浦」方法做為基礎,利用操作頻率的不同來定性並定量的研究在介電層中缺陷分布的情形。通道電子能穿隧的深度會隨著不同操作頻率而改變,因此可由電荷幫浦電流對應到頻率便能得知在閘極介電層中不同深度的缺陷密度。 此方法用來觀察由製程造成閘極介電層缺陷,另外我們也研究在高介電層中嚴重的N通道元件正壓高溫破壞後的不穩定性。在不同操作破壞條件下觀察缺陷產生情形,並將此結果與電性有效對應,如臨界電壓、汲極電流等。藉由電荷幫浦方法,我們可以了解在不同製程以及不同操作條件下介電層的良好程度,電路操作的可靠度問題,並且對其物理機制有更深入的了解。 | zh_TW |
dc.description.abstract | With the aggressive scaling of CMOS devices, SiO2-based gate dielectrics can’t conform the demand of low power application due to large gate leakage and high-k materials as the alternative of SiO2-based gate dielectrics has attracted a lot of interest. Recently, the studies indicate that HfSiON dielectric significantly reduces gate leakage by increasing physical thickness. Compared to the conventional SiO2 or SiOxNy gate dielectrics, Hf-based gate dielectrics are well known to suffer from the serious reliability concern of threshold voltage shifts and operation current instability due to the fast charge trapping and de-trapping in the pre-existing bulk traps in high-k bulk layer. Therefore, it is very important to develop a integrated and reliable method to quantitatively characterize charge traps in high-k dielectrics. In this thesis, proposed “Charge Pumping” approach is well developed and we will utilize it basically to study the traps distribution in dielectrics qualitatively and measurably. The available tunneling depth of channel carriers is dependent of frequency. Hence traps density in opposition to dielectric depth is extracted by charge pumping current and frequency. This method will be used to profile gate dielectrics traps induced by different process. Besides, positive bias temperature instable (PBTI) in high-k gate dielectric nMOSFETs is a critical issue and we will study it. In distinct stress condition, the traps generation will be powerfully related to characteristic in circuit level, such as threshold voltage and drain current. By charge pumping method, the quality and reliability of dielectrics in different process and distinct operation is distinguished and the physics behind is more understood. | en_US |
dc.language.iso | zh_TW | en_US |
dc.subject | High-k gate dielectric | zh_TW |
dc.subject | trap density | zh_TW |
dc.subject | 高介電常數介電層 | en_US |
dc.subject | 缺陷密度 | en_US |
dc.title | 以鉿為基底之高介電常數閘極介電層之N通道金氧半電晶體可靠度探討 | zh_TW |
dc.title | Investigation of Reliability in Advanced Hf-Based High-k Gate Dielectrics nMOSFETs | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |