10Gbps自動增益控制電路

Abstract

近年來隨著半導體製程的不斷演進，以及大眾對於功率效能的需求，使得多核心運算成為實現高資料運算量的處理平台主流之一；而由於光纖傳輸具有低串音(Cross Talk)以及低電磁干擾(EMI)的特性，被視為適合應用於此類高密度高速率的資料傳輸媒介。因此，在互補式金屬氧化物半導體(CMOS)製程下實現小面積、低成本的光纖收發機電路，以期應用於高密度傳輸平台之系統單晶片設計，成為富有挑戰性以及實用性的研究主題。 為實現一個可使用脈衝振幅調變(Pulse Amplitude Modulation, PAM)的光纖接收端前級電路，增益變異的功能對輸入動態範圍有其存在的必要性；又為克服傳統全類比自動增益控制電路所面對之挑戰，如增益控制線性度不足、反應時間過長等，本論文提出一個無電感下資料傳輸速率達10Gbps，以數位方式控制增益的自動增益控制系統，並期待能應用於低電壓架構以及先進製程。 內含之可調增益放大器之部份，提出巢狀主動回授架構來增加傳輸頻寬，且使其轉移函式符合貝索濾波器(Bessel Filter)響應，以減少群體延遲(Group Delay)變異量；並以數位方式控制輸入級源級退化阻值以改變等效轉導值，藉此改變放大器增益。再利用數位電路實現具有-二分搜尋/線性搜尋-雙模式的增益控制電路，達到快速鎖定、長時穩定的設計考量。 為了使輸出電壓擺幅能在需求範圍之內，電路中也包含了輸出擺幅峰值偵測器(Peak Detector)以及比較器，來鎖定擺幅極大值並且和參考電壓值進行比較。電壓偵測器中利用數位電路設置了開關機制來減少重置時間(Reset Time)以及趨穩時間(Settling Time)；比較器亦使其具有遲滯效應(Hysteresis Effect)，避免雜訊干擾以及增益調整解析度的有限造成電路不穩。 測試晶片使用標準0.18μm CMOS製程來製造。在1.8V的操作電壓之下，量測到的資料傳輸速率可達約8Gbps，輸入動態範圍為22dB，二分搜尋鎖定時間為170ns；在24位元溫度計碼的控制之下，增益控制解析度可達0.9dB/bit；晶片大小為620x620μm2 ，總功率消耗為86.4mW。

Recently, with the progress of the semi-conductor technology, and the demand of power efficiency, multi-cores computation becomes one of the mainstreams to realize a high speed processing platform. Due to the slight cross talk and low EMI properties, optical links are believed to be the suitable media for this high speed, high density data transmission. As a result, implementation of optical transceiver in CMOS technology with small form factor and low cost becomes a challenging and practical research topic for the SOC design of the high density communication platform. To implement an optical receiver front-end which is suitable for PAM (Pulse Amplitude Modulation), a mechanism of gain variation is indispensable for an input dynamic concern. Furthermore, to overcome the problems of conventional analog AGC (Automatic Gain Control) circuit, such as the gain non-linearity or long response time, an inductor-less, 10Gbps, digitally gain-controlled AGC circuit is proposed in this thesis, and prospected to be applied in low voltage design and advanced process. In order to enhance the bandwidth of the amplifier, nested active feedback architecture is proposed in the VGA (Variable Gain Amplifier) design, and its transfer function is corresponded with a Bessel type filter response, to alleviate group delay variation. For gain variation, the source degeneration resistance of input stage is controlled digitally and hence the equivalent transconductance. Moreover, the gain-controlled circuit with dual mode, binary search and linear search, is implemented by digital circuit for the design consideration of fast locking and being steady in the lone run. To keep the output swing in the range of requirement, there are peak detector and comparator in this AGC, for utilities of peak amplitude acquisition and comparing to the reference voltage. In the peak detector, switches are adopted to reduce the reset time and settling time with digital control signal; and the comparator with Hysteresis effect can avoid the instability caused by noise and finite resolution of gain control. The test chip is implemented in standard 0.18μm CMOS technology. Under 1.8V operating voltage, the measured data rate is about 8Gbps; input dynamic range is 22dB, with 170ns binary search settling time. With 24 bits thermometer code, gain-controlled resolution is 0.9dB/bit. Chip size is 620x620μm2, and total power consumption is 86.4mW.