可平行順序輸入及輸出快速傅立葉轉換處理器之設計

Abstract

為了設計一個具有可平行輸入及平行輸出的快傅立葉轉換處理器以適用於高速移動無線都會型區域網路(WMAN)基頻接收器中的通道估測方法，本論文由硬體設計層級研究各種可平行輸入及平行輸出的快速傅立葉轉換硬體架構技術。同時，為了簡化快速傅立葉轉換電路的資料串列輸入及資料串列輸出所需的控制訊號複雜度及暫存器使用，本論文提出一個可依序平行輸入及平行輸出的快速傅立葉轉換電路，以符合系統對快速傅立葉轉換處理器的輸入輸出規格要求。最後，本論文提出一個可適用於802.16e通訊系統中離散傅立葉通道估測法(DFT-based channel estimation)的可平行順序輸入及平行順序輸出之快速傅立葉轉換處理器的架構設計。並且根據離散傅立葉通道估測法中對快速傅立葉轉換的特殊需求，提出一個可適用於此通道估測法的部份傅立葉轉換(Partial FFT)架構設計。最後，本論文所提出的快速傅立葉轉換處理器已實現於一個2×1 STBC/OFDMA 基頻接收器中。此傅立葉轉換處理器可達到最高1.28 G 樣本/秒的資料吞吐量；當操作在最大工作頻率160 MHz下，其資料延遲時間僅需7.3 us；當操作在系統給定頻率78.4 MHz下，此傅立葉轉換電路消耗功率為21.7 mW，面積為155792 邏輯閘數(包含記憶體)，使用90奈米1V CMOS製程下，其面積為0.545 mm2。

In order to design a parallel-in-parallel-out Fast Fourier Transform (FFT) processor suitable for channel estimation in a highly mobile wireless metropolitan area network (WMAN) baseband receiver, this thesis studies various parallel-in- parallel-out FFT design techniques from hardware architecture level. Also, in order to reduce the control complexity and buffer overhead for data stream-in and stream-out of the FFT processor, this thesis proposes a FFT processor with parallel-in- parallel-out in normal order to meet the input data and output data requirement for the systems requirement. Finally, this thesis proposes a 1024-point FFT processor architecture with parallel-in-parallel-out in normal order, which can meet the needs of DFT-based channel estimation in 802.16e communication system. Furthermore, according to the special requirement of the DFT-based channel estimation, the thesis proposes the partial FFT processor architecture suitable for the DFT-based channel estimation. The FFT/IFFT processor is designed and is implemented together with a 2×1 STBC/OFDMA baseband receiver. The proposed 1024-point FFT/IFFT processor can achieve the throughput rate up to 1.28 G samples/sec and the execution time down to 7.3 us when working at 160 MHz. When working at the system required 78.4 MHz, it consumes 21.7 mW with 155792 gates (including memory) that occupy 0.545 mm2 by using 90 nm, 1V CMOS process.