應用於全球互通微波存取通訊協定的面積優化雙位元迴旋渦輪解碼器

Abstract

本論文介紹一個雙位元迴旋渦輪解碼理論，同時提出了一個應用於全球互通微波存取通訊協定符合所有種類的面積優化解碼器。我們提出的解碼器可以支援所有定義在IEEE 802.16e規格裡的編碼長度。藉由等比例縮減外在資訊，MAX-Log MAP演算法可以在極小的效能降低下減低硬體複雜度。另外提出了假雙埠暫存檔案可以大量的省下記憶體的使用量以及解碼時所產生的延誤並且允許同時讀取及寫入資料在同一個解碼週期內。除此之外，我們所提出的簡化過後的交錯器只用到了簡單的加法及減法器可以大量的減少硬體的使用量。根據實驗結果，此解碼器在90nm製程下最高能達到30Mb/s的傳輸速度，晶片的面積是1.12mm2。此外，在0.9V的供應電壓、166MHz操作頻率以及編碼長度2400下，功率的消耗經量測過後為32.87mW。

本論文另外提供了一個應用隨機更新規則的柵狀解碼理論。藉由使用了隨機運算方式，ACS單位的硬體複雜度可以大大的被簡化。所提出的狀態記憶體增加了隨機切換活動力可避免鎖定在同一個固定的狀態，以及所引用的等比例降低雜訊相依因子可以消去地板錯誤現象。這兩種技術階可讓解碼性能大突的提高。相較於 (2, 1, 3) 的渦輪碼，實驗結果顯示隨機解碼器可以是一個做為降低硬體複雜度的解碼選項。

Double-binary convolutional turbo code (CTC) decoding algorithm is introduced in this thesis, and a fully compliant and area-efficient CTC decoder for WiMAX 802.16e is proposed. The proposed decoder can support all code lengths specified in IEEE 802.16e system. By scaling the extrinsic information, the Max-Log MAP algorithm is used such that hardware complexity can be reduced with the minimized performance loss. For saving memory requirement and reducing decoding latency, the pseudo two-port register file is also demonstrated to allow read and write operation within one decoding cycle. Moreover, a simplified interleaver architecture which uses simple addition and subtraction instead of division is proposed to reduce the hardware area and decrease the critical path. Implemented in the 90-nm process, the proposed decoder chip occupied in 1.12mm2 core area can achieve 30Mb/s decoding throughput. The power consumption according to post-layout simulation is 32.87mW operated at supply voltage 0.9V and clock rate 166MHz with block length of 2400.

Another trellis-based decoding algorithm using stochastic update rule is also presented in this thesis. By using the stochastic computation, the hardware complexity can be reduced by simplifying ACS-unit operation. The proposed state memory can increase the random switching activity to avoid the state locked into a fixed state, and noise dependent scaling factor can further eliminate the error floor effect. Both techniques can greatly improve the performance compared to the Viterbi decoding algorithm. Through the simulation analysis and parameter decision for (2, 1, 3) convolutional code, the performance comparison shows that the stochastic decoding algorithm can be one of the candidates for low complexity iterative decoding.