IEEE 802.16e 正交分頻多重存取系統發射機之基頻電路設計

Abstract

為了設計一個具低複雜度、低成本、用於IEEE 802.16e標準的正交分頻多重存取發射器，本論文先研究IEEE 802.16e-OFDMA模式的實體層中各個區塊的功能，另外並涉獵各種適用於發射器的電路區塊，其中發現快速傅立葉轉換器是發射器最消耗硬體資源的區塊。在資料上鏈傳輸中，使用者端經常只被分配到一部份的子載波，因此不用執行全部點數的快速傅立葉轉換。然而在過去，當快速傅立葉轉換的輸入點為稀疏不規則分佈時的情形，並沒有相關快速傅立葉轉換器被提出以減少運算量。因此我們提出兩個在此種情形減少運算量的新方法。第一個方法消除所有與零相關的運算，第二個方法架構在第一個方法上，並且藉由觀察到當輸入點為稀疏時，並以特殊次序執行快速傅立葉蝴蝶單元時，前後兩個蝴蝶單元的輸入常具有高相關性，而此高關聯性可以被運用以進一步減少運算量。這兩個演算法並實際以硬體實作以分析功率消耗。 在建構發射器的過程中，一個發射器的軟體模型先被建立，接著加以實作。發射器裡交錯器經過優化而只需要小晶片面積，而且信號的切換頻率也少許多。另外，發射器裡記憶體的架構被重排而大大減少記憶體所需的面積。最後整個發射器在可程式化邏輯晶片中建模以驗證功能，並且以聯電0.18微米製程合成。

In order to design a low-complexity and low-cost IEEE 802.16e-OFDMA baseband transmitter for subscriber station, the thesis first studies the PHY layer functions of the IEEE 802.16e WirelessMan-OFDMA PHY standard. Various architectures for the critical function blocks of the transmitter are also studied; among them, the FFT processor is the most hardware-consuming element. In the uplink transmission, a subscriber station may only be allocated part of the subcarriers so that full computation of IFFT is unnecessary. However in the past, there has been no any related research on how to implement the FFT processor when the input is sparse and irregularly distributed. Two novel partial-input FFT algorithms then are proposed to compute the FFT algorithms efficiently when input is sparse and irregularly distributed. Firstly, based on the conventional FFT algorithm, we proposed an improved partial-input FFT algorithm, called removed-zero partial-input FFT algorithm (RZ-PFFT), which eliminates all the redundant memory accesses and multiplication operations associated with the zero operands due to sparse inputs. The second proposed algorithm, called removed-zero-and-correlation partial-input FFT algorithm (RZC-PFFT), further improves the RZ-PFFT algorithm and reduces multiplication operations by utilizing the correlation between the complex multiplications of two consecutive butterfly operations. This correlation is introduced by the increased number of zero operands in the FFT SFG. Both proposed algorithms are tailored for easy hardware implementations and is realized and synthesized using 0.18μm UMC 1P6M CMOS process. The synthesized RZ-PFFT and RZC-PFFT processors have area of 1.99 mm2 and 2.12 mm2, respectively. Their execution time for the 2048-point FFT is 230us at operating frequency of 100 MHz. In the implementation of the baseband transmitter for the subscriber station, a Matlab model is first constructed, and then the baseband transmitter is realized. The interleaver of the transmitter is optimized to have small-area and less signal transitions; also, the memory architecture for the storage of data before performing IFFT is reorganized to save significant memory size. Finally, the transmitter is prototyped on Altera’s FPGA board, and it consumes small FPGA resources; when synthesized using 0.18μm CMOS process, it has gate count of 307215.